M5 Max / RTX 3080 Ti FP32 benchmark
Frozen source 16413afeba4483f71f72350e8bfcd4594fb9186d; origin/main at measurement f72d046229bb27038da4748765b9fa38e9262e70.
What this measures
The same cached Q1, continuing-QH, and 20-frame EVL transactions ran three fresh trials with three warmups and ten synchronized operations per trial. The 180 displayed timings are descriptive host-runtime measurements. p10/p90 ranges are quantiles of correlated timed operations, not confidence intervals.
Training measures forward, loss, backward, clipping, and unfused AdamW update. EVL measures frozen eval inference; cached input mapping, model construction, loads, and transfers are outside the steady-state timer.
Latency results
| Workload | CUDA median (s) | MPS median (s) | MPS / CUDA latency |
|---|---|---|---|
| Q1 | 0.938 | 3.590 | 3.83× |
| Continuing | 2.329 | 7.546 | 3.24× |
| Evl | 0.242 | 5.202 | 21.46× |
The ratio compares the configured host runtimes, including named CPU fallbacks where present.
All timed operations
Each path is one trial; Seaborn draws raw ordered observations with no estimator, bootstrap, or error band.
Hardware and precision
| Receipt | Device | Platform | Torch |
|---|---|---|---|
| q1 MPS | Apple M5 Max | macOS-26.6.2-arm64-arm-64bit | 2.4.1 |
| q1 CUDA | NVIDIA GeForce RTX 3080 Ti | Linux-7.0.0-38-generic-x86_64-with-glibc2.43 | 2.4.1+cu121 |
| continuing MPS | Apple M5 Max | macOS-26.6.2-arm64-arm-64bit | 2.4.1 |
| continuing CUDA | NVIDIA GeForce RTX 3080 Ti | Linux-7.0.0-38-generic-x86_64-with-glibc2.43 | 2.4.1+cu121 |
| evl MPS | Apple M5 Max | macOS-26.6.2-arm64-arm-64bit | 2.4.1 |
| evl CUDA | NVIDIA GeForce RTX 3080 Ti | Linux-7.0.0-38-generic-x86_64-with-glibc2.43 | 2.4.1+cu121 |
FP32, highest matrix precision, disabled CUDA TF32, and unfused/non-foreach AdamW are validated from the receipts. Allocator and RSS measurements remain host-native and are not cross-backend memory comparisons.
Fallback and evidence limits
- q1 / MPS: aten::_linalg_det.result
- q1 / CUDA: none
- continuing / MPS: aten::_linalg_det.result
- continuing / CUDA: none
- evl / MPS: aten::_upsample_bicubic2d_aa.out
- evl / CUDA: none
EVL learned occupancy and centerness vary within host because its upstream lifter samples depths randomly. Logical workload fields and input hashes remain stable; this is neither prediction accuracy nor cross-backend numerical equivalence.
Operating status: all six benchmark receipts completed successfully. The historical CUDA–MPS numerical gate failed at source 65559e7aa13acc76f05ec897f40d7e2fa52b7f8a and was not retested by this later 16413 timing study. This report does not rerun the gate, promote equivalence, admit a Mac-generated corpus, establish full training-fit throughput, or claim deployment readiness.
Receipt identity
Six raw receipt hashes, the timing CSV, EVL input manifest, renderer hash, and SVG asset hashes are sealed in report-snapshot.json. The raw benchmark receipts remain the source of numeric truth.